U.S. Pat. No. 5,463,340 discloses a shift register comprising a chain of master-slave stages. In operation clock signals are provided first to copy data between stages and next to copy data within the stages from a master flip-flop to a slave flip-flop that supplies the data to the output of the stage. Thus, data in the slave flip-flops is always overwritten only after it has been copied to the master flip-flop of the next stage.
U.S. Pat. No. 5,463,340 uses four control signals derived from a clock signal to control each shift register stage, two for the master flip-flop and two for the slave flip-flops. In each flip-flop, the control signals control a pass and a hold function respectively. The four control signals are generated by applying the clock signal to a chain of inverters and using control signals from the outputs of respective ones of the inverters.
However, such a way of generating control signals may not be reliable if a large number of shift register stages has to be controlled. The effectiveness of the control signal may depend on the data in the stages.